Adaptation of technology to meet the needs of end users

Analog Expertise

Basic Analog
Filters, Signal chain blocks, amplifiers, equalizers,comparators, op-amps, regulators


10s-GPIO, HSIO, LVDS, Audio Interface, Display Port
Links - MIPI, DDR(1to4), USB(2/3), PCI-gen(2/3), HDMI, Bluetooth

Timing Blocks Synchronizers, Clock (Generator, Buffer, Divider,Clock Tree), PLL(Low Jitter), DLL, CDR, Oscillators low power, LC, Ring), Jitter Attenuator, VCO. Phase Interpolators (Mus, Mixer, Driver)

Power Managements Bandgap, BGRS, DC-DC Convertors, Buck- Boost, LDO, Charge Pump, Ref Circuits, POR, High Voltage, High Power, Master Bias, iref-gen.

RF Power Amplifiers, Switches, Pre-Drivers, Transmitter, Receiver, Baseband, Transmission line, Clock Distribution, RFID Transponders

Data Processing ADC, DAC, Audio Codec, Filters, Current Steering RDACs, Rail-To-Rail

Miscellaneous ESD, Latch-up, Bond Pad, ESD Pad, Process monitors, Clamps, Fuse

Others Drivers, Sensors, MEMS

Embedded System Expertise

Phytec SOM

Arm core A8 Processor

Fujistu FM3 MB9AF312

Infineon pXMC302


Calixto SOM Module

Renesas R12


Embedded Expertise

Eclipse - IDE


Logical Analyzer MPLAB

IAR Workbench

Embedded Skills

CAN protocols



Raw socket communication Multithreading



OTA Over MQTT and HTTP(over Wifi)

Design Using Rhapshody

RTC Integration

Physical Verification Expertise

Full Chip, Sub-System and block level verification

Expertise in Full chip Sign-off

Tool Expertise: Calibre, IC Validator, PVS, ICCI, ICC2, Innovus

LVS, DRC, Antenna, Density, DFI Integra, DRC ipall, denaliphem!, dredbase, RV fixes, dredvlup and other bundle flows.

RV fixes implementation on partition received through tel files for pwr/gnd and signal improvements for Timing Closure

Digital Expertise

Common Design

SRAM(SP,DP, Multi-Megahit SRAM)

Register Files (DP, MP, 1R1W, 182W, 2R2W, 2R3W, 3R3W)

CAM (TLBL. TLBS, PTAG, LUT, Read Table, Translation Buffers).

Cache (L1, L2, Monitors, Shift Registers, Queues) Includes ABIST engine, OPCG, GPTR, NCLK ROM (Metal Fuse, Programming)

ROM(Metal Fuse, Programming)


Library Development

Standard Cell Multi-track Design, High Power, High Density.

High Speed, High Performance, Architecture developments

IO Leaf Cells Pre-decoder, Decoder.

Memory Basic Cells Pre-decoders, Decoder, Latches, Mux,Comparators, Switches

Physical Verification

Flow Checks LVS, DRC, Density, Yield, Sanity Checks, Technology Specific

Reliability Checks EM, IR, ESD and Others

Physical Design Expertise


Synopsys ICC, ICC2, Prime Time, StarRC, Formality, PrimeTime SI

Cadence - SOC Encounter, Voltus, Vstorm, Innovus

Mentor - Olympus, Calibre

Apache - Redhawk, Totem Pathfinder

Dorado -Tweaker

Magma -Talus

Automation And QA

Period and Financial closing support.

Perl scripting

TCL scripting

Shell Scripting

QA Infrastructure development using Peri

Physical Design Expertise

Floor plan, Power Plan, IO plan, Physical Synthesis, Static Timing Analysis, Clock Tree Synthesis, Place and Route, Timing Closure LVS, DRC, DFM, Cross talk Analysis, Antenna fixes, EM, IR Drop Analysis, SI Analysis, ECO Implementation.

PaR execution for multiple SOC, IP level and blocks

Synthesis and Verification Power, Performance, Area optimization

From Netlist to GDS Power Integrity for AMS

Timing ECO implementation, Timing closure

Multiple Tape-out experience

ASIC Design Flow Methodologies